Programs

Learning gem5 Tutorial and Coding Sprint (615B)

HiPINEB: Interconnection Networks in the Exascale and Big-Data Era (417A)

HiPINEB: Interconnection Networks in the Exascale and Big-Data Era (417A)

An Introduction to OpenPiton, a Manycore Open Source Processor  (617)

Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources
Jayesh Gaur, Intel
Mainak Chaudhuri, Indian Institute of Technology Kanpur
Pradeep Ramachandran, MulticoreWare Inc/Intel
Sreenivas Subramoney, Intel

NCAP: Network-Driven, Packet Context-Aware Power Management for Client-Server Architecture
Mohammad Alian, UIUC
Ahmed Abulila, UIUC
Lokesh Jindal, University of Wisconsin-Madison
Daehoon Kim, UIUC/DGIST
Nam Sung Kim, UIUC

Supporting Address Translation for Accelerator-Centric Architectures
Yuchen Hao, UCLA
Zhenman Fang, UCLA
Glenn Reinman, UCLA
Jason Cong, UCLA

Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques
Yu Cai, Seagate Technology
Saugata Ghose, Carnegie Mellon University
Yixin Luo, Seagate Technology
Ken Mai, Carnegie Mellon University
Onur Mutlu, ETH Zurich/CMU
Erich Haratsch, Seagate Technology

Defect Analysis and Cost­effective Resilience Architecture for Future DRAM Devices
Sanguhn Cha, Samsung Electronics
Seongil O, Samsung Electronics
Hyunsung Shin, Samsung Electronics
Sangjoon Hwang, Samsung Electronics
Kwangil Park, Samsung Electronics
Seong Jin Jang, Samsung Electronics
Joo Sun Choi, Samsung Electronics
Gyo Young Jin, Samsung Electronics
Young Hoon Son, Samsung Electronics
Hyunyoon Cho, Samsung Electronics/Seoul National University
Jung Ho Ahn, Seoul National University
Nam Sung Kim, University of Illinois Urbana-Champaign

Architecting an Energy­Efficient DRAM System For GPUs
Niladrish Chatterjee, NVIDIA
Mike O’Connor, NVIDIA
Donghyuk Lee, NVIDIA
Daniel R. Johnson, NVIDIA
Stephen W. Keckler, NVIDIA
Minsoo Rhu, NVIDIA
William J. Dally, NVIDIA

Design and Analysis of an APU for Exascale Computing
Vijay Thiruvengadam, AMD Research
Yasuko Eckert, AMD Research
Gabriel Loh, AMD Research
Michael Schulte, AMD Research
Mike Ignatowski, AMD Research
Indrani Paul, AMD Research
Brad Beckmann, AMD Research
Steven Reinhardt, AMD Research
William Brantley, AMD Research
Joseph Greathouse, AMD Research
Onur Kayiran, AMD Research
Matthew Poremba, AMD Research
Wei Huang, AMD Research
Arun Karunanithi, AMD Research
Greg Sadowski, AMD Research
Vilas Sridharan, AMD Research
Steven Raasch, AMD Research
Mitesh Meswani, AMD Research

BRAVO: Balanced Reliability­Aware Voltage Optimization
Karthik Swaminathan, IBM T. J. Watson Research
Nandhini Chandramoorthy, IBM T. J. Watson Research
Chen­Yong Cher, IBM T. J. Watson Research
Ramon Bertran, IBM T. J. Watson Research
Alper Buyuktosunoglu, IBM T. J. Watson Research
Pradip Bose, IBM T. J. Watson Research

Maximizing Cache Performance Under Uncertainty
Nathan Beckmann, CMU
Daniel Sanchez, MIT

SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum
Hardware Support
Xiaodong Wang, Cornell University
Shuang Chen, Cornell University
Jeff Setter, Stanford University
José F. Martínez, Cornell University

A Split Cache Hierarchy for Enabling Data-oriented Optimizations
Andreas Sembrant, Uppsala University
David Black-Schaffer, Uppsala University
Erik Hagersten, Uppsala University

Fast and Accurate Exploration of Multi-Level Caches Using Hierarchical Reuse Distance
Rafael K. V. Maeda, Hong Kong University of Science and Technology
Qiong Cai, Hewlett Packard Labs
Jiang Xu, Hong Kong University of Science and Technology
Zhe Wang, Hong Kong University of Science and Technology
Zhongyuan Tian, Hong Kong University of Science and Technology

Enabling Effective Module-oblivious Power Gating for Embedded Processors
Hari Cherupalli, University of Minnesota
Henry Duwe, University of Illinois
Weidong Ye, University of Illinois
Rakesh Kumar, University of Illinois
John Sartori, University of Minnesota

Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices
Karthik Rao, Georgia Institute of Technology
Jun Wang, Huawei US R&D
Sudhakar Yalamanchili, Georgia Institute of Technology
Yorai Wardi, Georgia Institute of Technology
Handong Ye, Huawei US R&D

Fast Decentralized Power Capping for Server Clusters
Reza Azimi, Brown University
Masoud Badiei, Harvard University
Xin Zhan, Brown University
Na Li, Harvard University
Sherief Reda, Brown University

Random Folded Clos Topologies for Datacenter Networks
Cristóbal Camarero, University of Cantabria
Carmen Martínez, University of Cantabria
Ramón Beivide, University of Cantabria

Tiny Directory: Efficient Shared Memory in Many-core Systems with Ultra-low-overhead Coherence Tracking
Sudhanshu Shukla, Indian Institute of Technology Kanpur
Mainak Chaudhuri, Indian Institute of Technology KanpurPartial Row Activation for Low-Power DRAM System
Yebin Lee, Korea Advanced Institute of Science and Technology (KAIST)
Hyeonggyu Kim, Korea Advanced Institute of Science and Technology (KAIST)
Seokin Hong, Samsung Electronics Co., Ltd.
Soontae Kim, Korea Advanced Institute of Science and Technology (KAIST)

Understanding and Optimizing Power Consumption in Memory Networks
Xun Jian, University of Illinois
Pavan Kumar Hanumolu, University of Illinois
Rakesh Kumar, University of Illinois

SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies
Hasan Hassan, ETH Zurich/TOBB University of Economics & Technology/CMU
Nandita Vijaykumar, Carnegie Mellon University
Samira Khan, University of Virginia/CMU
Saugata Ghose, Carnegie Mellon University
Kevin Chang, Carnegie Mellon University
Gennady Pekhimenko, Carnegie Mellon University / Microsoft Research
Donghyuk Lee, NVIDIA Research/Carnegie Mellon University
Oguz Ergin, TOBB University of Economics & Technology
Onur Mutlu, ETH Zurich/CMU

Static Bubble: A Framework for Deadlock-free Irregular On-chip Topologies
Aniruddh Ramrakhyani, Georgia Institute of Technology
Tushar Krishna, Georgia Institute of Technology

Designing Low-power, Low-latency Networks-on-Chip by Optimally Combining Electrical and Optical Links
Sebastian Werner, The University of Manchester
Javier Navaridas, The University of Manchester
Mikel Luján, The University of Manchester

Near-Ideal Networks-on-Chip for Servers
Pejman Lotfi-Kamran, Institute for Research in Fundamental Sciences (IPM)
Mehdi Modarressi, University of Tehran/Institute for Research in Fundamental Sciences (IPM)
Hamid Sarbazi-Azad, Sharif University of Technology/Institute for Research in Fundamental Sciences (IPM)

Design and Evaluation of AWGR-based Photonic NoC Architectures for 2.5D Integrated High Performance Computing Systems
Paolo Grani, University of California, Davis, Electrical and Computer Engineering Department
Venkatesh Akella, University of California, Davis, Electrical and Computer Engineering Department
Roberto Proietti, University of California, Davis, Electrical and Computer Engineering Department
S. J. Ben Yoo, University of California, Davis, Electrical and Computer Engineering Department

Secure Dynamic Memory Scheduling Against Timing Channel Attacks
Yao Wang, Cornell University
Benjamin Wu, Cornell University
Edward Suh, Cornell University

Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors
Salessawi Ferede Yitbarek, University of Michigan
Misiker Tadesse Aga, University of Michigan
Reetuparna Das, University of Michigan
Todd Austin, University of Michigan

Cooperative Path-ORAM for Effective Memory Bandwidth Sharing in Server Settings
Rujia Wang, University of Pittsburgh
Youtao Zhang, University of Pittsburgh
Jun Yang, University of Pittsburgh

Camouflage: Memory Traffic Shaping to Mitigate Timing Attacks
Yanqi Zhou, Princeton University
Sameer Wagh, Princeton University
Prateek Mittal, Princeton University
David Wentzlaff, Princeton University

SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization
Jee Ho Ryoo, UT-Austin
Mitesh R. Meswani, ARM
Andreas Prodromou, UCSD
Lizy K. John, UT-Austin

ATOM: Atomic Durability in Non-volatile Memory through Hardware Logging
Arpit Joshi, University of Edinburgh
Vijay Nagarajan, University of Edinburgh
Stratis Viglas, University of Edinburgh
Marcelo Cintra, Intel

KAML: A Flexible, High-Performance Key-Value SSD
Yanqin Jin, UCSD
Hung-Wei Tseng, UCSD/NC State University
Steven Swanson, UCSD
Yannis Papakonstantinou, UCSD

Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor
Mingzhe Zhang, Institute of Computing Technology, Chinese Academy of Sciences
Lunkai Zhang, University of Chicago
Lei Jiang, Indiana University
Bloomington Zhiyong Liu, Institute of Computing Technology, Chinese Academy of Sciences
Fred Chong, University of Chicago

Reliability-Aware Scheduling on Heterogeneous Multicore Processors
Ajeya Naithani, Ghent University
Stijn Eyerman, Intel
Lieven Eeckhout, Ghent University

Hipster: Hybrid Task Manager for Latency-Critical Cloud Workloads
Rajiv Nishtala, Barcelona Supercomputing Center
Paul Carpenter, Barcelona Supercomputing Center
Xavier Martorell, Barcelona Supercomputing Center
Vinicius Petrucci, Federal University of Bahia

Cooper: Task Colocation with Cooperative Games
Qiuyun Llull, Duke University
Songchun Fan, Duke University
Seyed Majid Zahedi, Duke University
Benjamin C. Lee, Duke University

MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-Level Memories
Andreas Prodromou, UCSD
Mitesh Meswani, ARM
Nuwan Jayasena, AMD
Gabriel H. Loh, AMD
Dean Tullsen, UCSD

Exploring Hyperdimensional Associative Memory
Mohsen Imani, University of California San Diego
Abbas Rahimi, University of California Berkeley
Deqian Kong, University of California San Diego
Tajana S. Rosing, University of California San Diego
Jan M. Rabaey, University of California Berkeley

GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks
Lifeng Nai, Georgia Institute of Technology
Ramyad Hadidi, Georgia Institute of Technology
Jaewoong Sim, Intel Labs
Hyojong Kim, Georgia Institute of Technology
Pranith Kumar, Georgia Institute of Technology
Hyesoon Kim, Georgia Institute of Technology

High-Bandwidth Low-Latency Approximate Interconnection Networks
Daichi Fujiki, National Institute of Informatics
Kiyo Ishii, National Institute of Advanced Industrial Science & Technology
Ikki Fujiwara, National Institute of Informatics
Hiroki Matsutani, Keio University
Hideharu Amano, Keio University
Henri Casanova, University of Hawaii at Manoa
Michihiro Koibuchi, National Institute of Informatics

Compute Caches
Shaizeen Aga, University of Michigan, Ann Arbor
Supreet Jeloka, University of Michigan, Ann Arbor
Arun Subramaniyan, University of Michigan, Ann Arbor
Satish Narayanasamy, University of Michigan, Ann Arbor
David Blaauw, University of Michigan, Ann Arbor
Reetuparna Das, University of Michigan, Ann Arbor

Boomerang: A Metadata-Free Architecture for Control Flow Delivery
Rakesh Kumar, University of Edinburgh
Cheng-Chieh Huang, University of Edinburgh
Boris Grot, University of Edinburgh
Vijay Nagarajan, University of Edinburgh

PABST: Proportional Allocation of Bandwidth at the Source and Target
Derek R. Hower, Qualcomm Research
Harold W. Cain, Qualcomm Research
Carl A. Waldspurger, Qualcomm Research

SOUP-N-SALAD: Allocation-oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures
Yuhwan Ro, Seoul National University
Hyunyoon Cho, Seoul National University and Samsung
Eojin Lee, Seoul National University
Daejin Jung, Seoul National University
Young Hoon Son, Samsung
Jung Ho Ahn, Seoul National University and Google
Jae W. Lee, Seoul National University

Transparent and Efficient CFI Enforcement with Intel Processor Trace
Yutao Liu, Shanghai Jiao Tong University
Peitao Shi, Shanghai Jiao Tong University
Xinran Wang, Shanghai Jiao Tong University
Haibo Chen, Shanghai Jiao Tong University
Binyu Zang, Shanghai Jiao Tong University
Haibing Guan, Shanghai Jiao Tong University

PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning
Linghao Song, University of Pittsburgh
Xuehai Qian, University of Southern California
Hai Li, University of Pittsburgh
Yiran Chen, University of Pittsburgh

FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks
Wenyan Lu, ICT,CAS
Guihai Yan, ICT,CAS
Jiajun Li, ICT,CAS
Shijun Gong, ICT,CAS
Yinhe Han, ICT,CAS
Xiaowei Li, ICT,CAS

Needle : Leveraging Program Analysis to Analyze and Extract Accelerators from Whole Programs
Snehasish Kumar, Simon Fraser University
Nick Sumner, Simon Fraser University
Vijaylakshmi Srinivasan, IBM Research
Steven Margerm, Simon Fraser University
Arrvindh Shriraman, Simon Fraser University

Radiation-Induced Error Criticality in Modern HPC Parallel Accelerators
Daniel Oliveira, UFRGS
Laércio Pilla, UFSC
Mauricio Hanzich, Barcelona Supercomputing Center
Vinícius Fratin, UFRGS
Fernando Fernandes, UFRGS
Caio Lunardi, UFRGS
José María Cela, Barcelona Supercomputing Center
Philippe Navaux, UFRGS
Luigi Carro, UFRGS
Paolo Rech, UFRGS

Pilot Register File: Energy Efficient Partitioned Register File for GPUs
Mohammad Abdel-Majeed, The University of Jordan
Hyeran Jeon, San Jose State University
Alireza Shafaei, University of Southern California
Murali Annavaram, University of Southern California
Massoud Pedram, University of Southern California

G-Scalar: Cost-Effective Generalized Scalar Execution Architecture for Power-Efficient GPUs
Zhenhong Liu, UIUC
Syed Gilani, AMD
Murali Annavaram, USC
Nam Sung Kim, UIUC

Dynamic GPGPU Power Management using Adaptive Model Predictive Control
Abhinandan Majumdar, Cornell University
Leonardo Piga, Advanced Micro Devices, Inc.
Indrani Paul, Advanced Micro Devices, Inc.
Joseph L. Greathouse, Advanced Micro Devices, Inc.
Wei Huang, Advanced Micro Devices, Inc.David H. Albonesi, Cornell University

Non-intrusive Persistence with a Backend NVM Controller
Libei Pu, Rice University
Kshitij Doshi, Intel Corporation
Ellis Giles, Rice University
Peter Varman, Rice University

Advanced Innovation Center for Imaging Technology
Weigong Zhang, Capital Normal University, Beijing Advanced Innovation Center for Imaging Technology
Xin Fu, University of Houston

Controlled Kernel Launch for Dynamic Parallelism in GPUs
Xulong Tang, Penn State
Ashutosh Pattnaik, Penn State
Huaipan Jiang, Penn State
Onur Kayiran, AMD Research
Adwait Jog, College of William and Mary
Sreepathi Pai, UT Austin
Mohamed Ibrahim, College of William and Mary
Mahmut Taylan Kandemir, Penn State
Chita Das, Penn State